This invention relates to a semiconductor integrated circuit comprising low-threshold complementary MIS (Metal Insulator Semiconductor) field effect transistors and, in particular, to a circuit structure intended for reduced power consumption in a sleep mode.
In a recent complementary MIS (Metal Insulator Semiconductor) logical LSI (Large-Scale Integrated circuit), each of MIS field effect transistors is reduced in gate length (L) so as to achieve an improvement in drivability of the transistor. Thus, an LSI chip having a high operation speed and a highly integrated structure is realized. With the reduction of the gate length (L), an operating source voltage is lowered in order to assure breakdown voltage and reliability of the transistor and to suppress the increase in power consumption of the whole chip due to the increase in device density.
Such a low source voltage results in a low operation speed of the logical circuit. Taking this into account, each of the field effect transistors (hereinafter abbreviated to FETs) forming the logical circuit is given a low-threshold voltage (Vt) whose absolute value (.vertline.Vt.vertline.) is small in conformity with the low source voltage. In this manner, the improvement in performance of the logical circuit is pursued in correspondence to scaling of the gate length (L).
However, such a MISFET having a low-threshold voltage (Vt) suffers an increase in leakage current (hereinafter called off current) while the FET is nonconductive. Therefore, in total power consumption of the logical circuit in an active mode and a sleep mode, the power consumption in the sleep mode tends to increase.
Referring to FIG. 1, consideration will be made about a P-channel MOS (Metal Oxide Semiconductor) FET (PMUS in the figure) and an N-channel MOSFET (NMOS in the figure) each of which has a gate length (L) of 0.25 .mu.m and an absolute threshold voltage (.vertline.Vt.vertline.) of 0.2V. When a gate width (W) is equal to 50 .mu.m, the off current (.vertline.Ioff.vertline.) on the order of 10 nA (=10.sup.-8 A) flows in each of the P-channel MOSFET (PMOS) and the N-channel MOSFET (NMOS). As seen from FIG. 1, the off current (.vertline.Ioff.vertline.) is reduced when a backgate bias voltage (.vertline.Vbs.vertline.) is increased. In FIG. 1, an abscissa and an ordinate represent the backgate bias voltage (.vertline.Vbs.vertline.) and the off current (.vertline.Ioff.vertline., respectively. It is assumed that a static leakage current of the whole chip has an upper limit of 1 .mu.A. In this event, the degree of integration of the transistors in the single chip is restricted within a range such that the total gate width of the transistors in an off state does not exceed 50 mm. Thus, with the increase in off current of the FETs following the reduction in gate length, the static leakage current of the whole chip becomes a factor determining the degree of integration of the transistors at a chip level. Since the value of the off current per unit gate width will hereafter be further increased following the reduction in gate length, it is predicted that the degree of integration of the FETs can not be increased in conformity with the scaling of the gate length (L).
Referring to FIG. 2, a semiconductor integrated circuit has a circuit structure intended for reduced power consumption of a logical circuit using low-threshold (Vt) transistors in a sleep mode. Such a semiconductor integrated circuit is disclosed, for example, in Japanese Unexamined Patent Publication (JP-A) No. 6-29834 (29834/1994). As illustrated in FIG. 2, a first power supply circuit comprises a high-threshold control transistor 16 arranged between a power supply line (VDD) 2 connected to a power supply 1 and a virtual or auxiliary power supply line (VVD) 3. On the other hand, a second power supply circuit comprises a high-threshold control transistor 17 arranged between a grounding line (GND) 6 and a virtual or auxiliary grounding line (VGD) 7 connected to the ground 5. A low-threshold logical circuit 15 has one power supply terminal connected to the virtual power supply line (VVD) 3 and the other power supply terminal connected to the virtual grounding line (VGD) 7. In order to stabilize electric potentials of the power supply lines and the grounding lines, capacitors 18-1 and 18-2 are connected between the power supply line (VDD) 2 and the virtual power supply line (VVD) 3 and between the grounding line (GND) 6 and the virtual grounding line (VGD) 7, respectively.
In the circuit structure illustrated in FIG. 2, the low-threshold logical circuit 15 is electrically fed from the power supply 1 through the high-threshold control transistors 16 and 17. In case of the above-mentioned MOSFETs having the gate length (L) of 0.25 .mu.m, the off current (.vertline.Ioff.vertline.) at the gate width (W) of 50 .mu.m can be reduced to a level on the order of 1 pA if the threshold voltage (Vt) of each of the high-threshold control transistors 16 and 17 is selected to be equal to 0.5 V. In the circuit structure of FIG. 2, the high-threshold control transistors 16 and 17 are turned off in the sleep mode (CS=low level, CSB=high level) to suppress a leakage current between the power supply 1 and the ground 5 to a low level. Thus, the power consumption in the sleep mode can be sufficiently suppressed as compared with that in an active mode.
In the above-mentioned circuit structure, however, it is required that at least one of the PMOS and the NMOS has two different threshold voltages (Vt), i.e., a high-threshold voltage and a low-threshold voltage. This results in increase in number of manufacturing steps.
On the other hand, each of the control transistors must have an ability of supplying an electric current necessary for the low-threshold logical circuit to operate at a desired operation speed under a low source-drain voltage (Vds). In the circuit structure mentioned above, high-threshold transistors sufficiently low in off current are used as the control transistors 16 and 17. In this event, each of the control transistors 16 and 17 must have a greater gate width as compared with the case where low-threshold transistors are used. This results in an unfavorable increase in layout area.
Referring to FIG. 3, another semiconductor integrated circuit with a power supply arrangement of the type illustrated in FIG. 2 is capable of holding information or data even in the sleep mode. This circuit is disclosed in S. Shigematsu et al "A 1-V High-speed MTCMOS circuit scheme for power-down applications", 1995 Symposium on VLSI Circuits Digest of Technical Papers, pages 125 and 126.
Referring to FIG. 3, connection between the low-threshold logical circuit 15 and the power supply circuits is similar to that described in conjunction with FIG. 2. In order to hold the data in an internal node (DATA) of the low-threshold logical circuit 15 even in the sleep mode, the low-threshold logical circuit 15 is connected to a latch circuit 19. The latch circuit 19 illustrated in FIG. 3 includes first and second inverters INV1 and INV2 comprising high-threshold transistors, and first and second transfer gates TG1 and TG2.
Referring to FIG. 4 in addition to FIG. 3, switching of the active mode and the sleep mode and a latching operation will be described.
In FIG. 4, the low-threshold logical circuit 15 and the latch circuit 19 are operated in the following manner.
In a first time interval T1, a normal operation is carried out. Both of the transfer gates TG1 and TG2 are turned off.
In a second time interval T2, the transfer gate TG1 is turned on while the transfer gate TG2 is turned off. The data in the DATA node in FIG. 3 is propagated into the latch circuit 19.
In a third time interval T3 which is a period in a sleep mode, the transfer gate TG1 is turned off while the transfer gate TG2 is turned on. The data held in the DATA node immediately before switching into the sleep mode is latched in the latch circuit 19.
In a fourth time interval T4, both of the transfer gates TG1 and TG2 are turned on. The data held in the latch circuit 19 are propagated into the low-threshold logical, circuit 15.
Thus, in the previous technique, the latch circuit as a data holding circuit for holding the data in the sleep mode is required in addition to the logical circuit. This brings about an increase in layout area. In addition, the operation of the data holding circuit is complicated as described in conjunction with FIG. 4. As compared with the case where the power supply arrangement in FIG. 2 is not used, the man-hour required in circuit design is increased.
Thus, these CMOS integrated circuits are disadvantageous in the following respects.
As a first disadvantage, the number of manufacturing steps and the production cost are increased.
This is because additional steps are required to set two kinds of threshold voltages, i.e., high and low threshold voltages. In order to set the threshold voltages, impurities are ion-implanted into a channel region of the MOSFET. In this event, two additional patterns are additionally required to set the high and low threshold voltages for each of the P-channel and the N-channel MOSFETs.
As a second disadvantage, the layout area of the control transistor in the power supply circuit is increased.
This is because, since the high-threshold transistor whose off current is sufficiently low is used as the control transistor of the power supply circuit, the gate width is great as compared with the case where the low-threshold transistor is used.
As a third disadvantage, the latch circuit for holding the data in the sleep mode is required in addition to the logical circuit. This brings about an increase in layout area, complexity in layout design and timing design, and an increase in man-hour for designing.